JOB DESCRIPTION:

Full time staff position

We are seeking mid to senior-level verification engineer who will be responsibilbe to drive verification of next generation solid-state enterprise storage and networking products.

Responsibilities:

• Hardware modeling using UVM, Verilog, System Verilog or C/C++
• Identify and isolate design issues
• Develop test plans and implement test benches
• Regression management

Qualifications:

• 6+ years of solid experience. At least 1 project starting to end.
• System Verilog based verification
• UVM/OVM/VMM or C++
• Coverage and assertions development and analysis
• Advanced verification methodologies using contrained random, assertion based verification
• Function and code coverage driven verification
• Proficient in version control (Subversion branching/revision management/tagging)
• Experienced in scripting (Perl) and C programming
• Knowledge of SoC architecture and verification, formal verification, post-silicon and lab debug
• Knowledge of SATA/SAS, PCIe, and Gigabit Ethernet
• Good written and oral communication skills (English)

Desired:

• PCI Express
• Flash

Education:

• BS in Computer Science or equivalent experienc

No Relocation | Local Candidates please

EEO/AA

No 3rd parties or agencies
unable to sponsor

DATE POSTED:

Previous Page | Home