JOB DESCRIPTION:

You will be responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly

Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout. Interface with other design groups to ensure time to market and quality of results.

You will also participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation.

The key to this job is STA or static timing analysis; we use a tool called Primetime

Qualifications

• 5+ years industry experience in a Logic design or Physical Design position.
• Strong knowledge of RTL design 
• Ffamiliar with RTL compiler/Design Compiler, ICC/SOC Encounter, Primetime, Conformal LEC, and ATPG.
• Working knowledge of scan insertion, and ATPG.
• Must have good communication, teamwork, and debug/analysis skills for designs, library and technology files.

Education:

BSEE/MSEE

EEO/AA

DATE POSTED:

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